1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a redundant circuit of a dynamic random access memory (DRAM).
2. Description of the Related Art
In recent years, a chip construction which is designed to permit a circuit to be commonly used by use of a multilayer interconnection is more frequently used with an increase in the memory capacity of the DRAM and an increase in the integration density.
The pattern layout of the chip construction in the conventional DRAM is shown in FIG. 1. That is, memory cells are divided into four memory cell arrays AL1 to AL4 and a column decoder CD and a sense amplifier (not shown) are provided for each of the memory cell arrays AL1 to AL4.
However, when the memory capacity of the memory is increased, the number of divided memory cell arrays must be increased and the chip area will be increased and the integration density cannot be increased if a column decoder CD is provided for each memory cell array in the same manner as in the chip construction shown in FIG. 1. Therefore, a chip construction having a pattern layout whose integration density is enhanced by additionally providing another interconnection layer and collectively disposing the column decoder CD and sense amplifier in one place as shown in FIG. 2 is more frequently used.
A recent DRAM includes a redundant circuit for remedying or compensating a defective chip by replacing defective memory cells of several bits to several thousand bits by spare memory cells which are preparatorily provided. The redundant circuit is a device for replacing a row line or a column line to which the defective memory cells are connected by a spare row line or spare column line provided in the same memory cell array in which the former row line or column line is provided in order to replace the defective memory cells by other memory cells which are provided as spare memory cells.
For example, in the column redundant circuit for replacing column lines, a spare column decoder which has a group of fuse elements and in which a column address can be programmed by cutting off specified fuse elements is provided and a spare memory cell can be selected by selecting the spare column line by use of the spare column decoder without selecting the defective memory cell when a column address corresponding to the defective memory cell is input. Likewise, in the row redundant circuit for replacing row lines, a spare row decoder which has a group of fuse elements and in which a row address can be programmed by cutting off specified fuse elements is provided and a spare memory cell can be selected by selecting the spare row line by use of the spare row decoder without selecting the defective memory cell when a row address corresponding to the defective memory cell is input.
FIG. 3 shows an example of the conventional column redundant circuit. That is, 11 denotes one of a plurality of partial column decoders provided in the column decoder CD, 12 denotes a logic circuit connected to the output side of the partial column decoder 11, and CDL denotes a column selection line supplied with a column selection signal via the logic circuit 12. Further, 13 denotes a column redundant circuit and SCDL denotes a spare column selection line supplied with a spare column selection signal from the column redundant circuit 13. A spare column line (not shown) to which spare memory cells (not shown) are connected is selected by a signal on the spare column selection line SCDL.
In the column redundant circuit 13, 14 denotes a programmable column decoder (spare column decoder) having a fuse element group and receiving a column address. In the spare column decoder 14, fuse elements are previously cut off to activate an output thereof if a defective memory cell is present and when a column address corresponding to the defective memory cell is input.
When a column address corresponding to a normal memory cell is input to the partial column decoder 11, the decoder output is supplied as a column selection signal to the column selection line CDL via the logic circuit 12. At this time, the decoder output from the spare column decoder 14 is set in the non-activated state. In contrast, when a column address corresponding to a defective memory cell is input, the decoder output of the spare column decoder 14 is set into the activated state and supplied as a spare column selection signal to the spare column selection line SCDL, and thus the defective memory cell is substantially replaced by a memory cell connected to the spare column selection line SCDL. Further, an output generated at this time from the spare column decoder 14 is input to the logic circuit 12 to set the output (column selection signal) of the logic circuit 12 into the non-activated state.
The maximum number of memory cells which can be remedied or compensated for by use of the above column redundant circuit is determined according to the number of spare memory cells. However, the number of memory cells which can be actually compensated for is largely dependent on the number of divided memory cell arrays, the number of column decoders, the number of column redundant circuits and the like. The column compensation rates in the chip constructions shown in FIGS. 1 and 2 are compared with each other. In the chip construction shown in FIG. 1, since a column decoder is provided for each memory cell array, a defective column line can be replaced by a spare column line for each memory cell array even when a defective column line is present in each of the memory cell arrays if a column redundant circuit is provided for each of the column decoders of the respective memory cell arrays. That is, when a chip having four column decoders as shown in FIG. 1 is used, one defective column line can be compensated for for each column decoder and four defective column lines at maximum can be compensated for. In contrast, in the chip construction shown in FIG. 2, since only one column decoder is provided and the column decoder simultaneously selects spare column lines with the same column address of the four memory cell arrays, only one defective column line in the four memory cell arrays can be compensated for if one column redundant circuit is provided for the column decoder, and therefore, the compensation rate is reduced to substantially 1/4 in comparison with a case of the chip construction shown in FIG. 1.
If four column redundant circuits are provided for each column decoder in the chip construction shown in FIG. 2, for example, in order to enhance the compensation rate, four defective column lines at maximum can be compensated for. In this case, however, four spare column lines must be provided for each memory cell array and a problem that the chip area will be increased occurs.
A problem similar to the above problem occurs when a row redundant circuit is provided in the chip construction in which the integration density is increased by commonly selecting four or more memory cell arrays by use of a single row decoder.